Data Converters
- Multichannel (>24 channels)
- High-speed (up to 1GS/s)
- High resolution (12-bit)
- Sigma-delta architecture (24-bit)
- 0.9/1.8-V, 500-MHz 2-bit ADC
PLL
- Low jitter 16GHz PLL
- Low jitter 28GHz PLL
- PLL veriloga Modeling for accurate jitter measurement
- 0.9-V, 1-mA, 2.5GHz Integer PLL
- 1.8-V, 0.5-mA, 578.4-MHz Fractional-N PLL for RFIC
- 1.2-V,2-mA 180nm SMIC 1.5GHz Integer PLL
- 1.2-V, 1÷16-mA,30÷3000-MHz Integer PLL
- 1.2-V, 1-mA,600-MHz Integer PLL
- 1.8-V, 1-mA 20÷200-MHz Integer PLL
RF
- A-class +3dBm power amplifier (2-2.5 GHz)
- Design of up-conv passive mixer with out-of-band suppression
- Design of A-class PA (75Mhz – 3 GHz)
- +10dBm E class PA with external components (100 – 920 MHz)
- Design of 3GHz LC VCO – SMIC CMOS 180nme
Data interface
- JESD204B analog TX/RX layers design– TSMC 28nm
- HSTL data interface – TSMC 28nm
- 1.8-V HSTL IO library
- 0.25-V 22nm SOI GF digital IO buffer
- 1.2-V 28nm TSMC 10G PHY for JESD204B
- 1.2/1.8-V 28nm TSMC 500MHz LVDS transceiver
- 0.9-V 28nm TSMC 2GHz low jitter CML receiver
- 0.9/1.8-V 28nm TSMC 50mW SGMII PHY (VGA/DFE/DigitalCDR/FFE/DRIVER/PLL) for 1G Ethernet
- 1.5/2.5-V 130nm SiGe GF 5G LTE/WiMAX Transceiver TX/RX BB Filters calibration
- 1.2-V, 60-uA 6-MHz RC clock generator
- 1.2-V, 0.5-mA 1.5GHz programmable serializer
Others
- Transimpedance amplifier (TIA) 28Gbit
- 0.9-V, 0.1-mA, 3σT=±2.5°C digital temperature sensor
- 1.8-V, 2-mA LDO voltage regulator
- 2.0/5.0-V 400mA 1.8V LDO Regulator
- 0.25-V to +/-2.1-V 22nm SOI GF voltage generator
- 0.3-V 10nm FinFET Samsung voltage level POR
- 250-V HBM ESD protection for Photonic devices
- 5.0-V 3σT=±15mv bandgap voltage reference
- 1.2-V, 50-uA POR